1. Field of the Disclosure
The present disclosure relates to a method of manufacturing semiconductor devices, and more specifically, to a method of manufacturing semiconductor devices having tungsten gates electrodes.
2. Brief Description of Related Technology
Of semiconductor memory devices, a flash memory device is characterized in that information stored in memory cells is not lost even if power is shut off. Accordingly, the flash memory device has been widely used in memory cards for use in computers, etc.
As a unit cell of the flash memory device, a memory cell having a structure in which a conduction film for floating gate and a conduction film for control gate are sequentially stacked has been widely known.
The conduction film for floating gate and the conduction film for control gate are generally formed using polysilicon. More particularly, a dual structure of a polysilicon film and a tungsten silicide (WSix) film is generally used as the conduction film for control gate.
As the degree of integration of flash memory devices increases, however, it is difficult to secure resistance in the dual structure of the polysilicon film and the tungsten suicide film. If a thickness is increased in order to secure resistance, there is a problem in that intra-capacitance is increased and inter-gate interference becomes high.
In view of the above, a method has been introduced in which a tungsten nitride (WN) film and a tungsten (W) film serving as barrier films are stacked instead of the tungsten silicide film (WSix), and the W film, the WN film and a lower layer are etched by means of a Reactive Ion Etching (RIE) method, thus forming a gate.
In the case where the gate is formed by the RIE method, it is difficult to deposit a spacer due to oxidization of tungsten when the spacer is formed in the gate sidewalls after the formation of the gate. There is also a problem in that reliability of the gate is degraded due to the shortage of thermal margin.
Accordingly, the damascene method has been proposed which will replace the RIE method.
In the damascene method, after a tunnel oxide film, a polysilicon film for floating gate and an interlayer dielectric film are formed on a semiconductor substrate, the interlayer dielectric film, the polysilicon film for floating gate and the tunnel oxide film are patterned by photolithography process. An interlayer insulation film is then formed to cover the entire surface. Trenches through which the interlayer dielectric film is exposed are formed in the interlayer insulation film. A polysilicon film for control gate, a barrier film and a W film are deposited within the trenches. The entire surface undergoes Chemical Mechanical Polishing (CMP) so that the interlayer insulation film is exposed, forming a gate.
If misalignment occurs upon etching of the trenches, however, the coupling ratio between the floating gate and the control gate reduces. Accordingly, there are problems in that the speed of the device is lowered and a voltage necessary for device operation increases.
Furthermore, as the degree of integration of memory devices increases and the gate width becomes narrow, the trench width reduces. In this case, the W film has to be deposited after the polysilicon film for control gate and the barrier film are formed within the narrow trenches. This results in a very degraded gap-fill characteristic of the W film.